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page 1 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com the PE4273 rf switch is designed for the tv tuner, pctv, set top box, dtv, dvr and general broadband applications. this device offers industry leading broadband linearity, 1.5 kv esd tolerance and a simple cmos interface. it offers a simple alternative solution to pin diode and mechanical relay switches. the PE4273 spdt broadband rf switch is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt broadband ultracmos ? 5 ? 3000 mhz rf switch product description figure 1. functional diagram PE4273 features ?? single-pin or complementary cmos logic control inputs ?? high esd tolerance of 1.5 kv ?? low insertion loss ?? 0.50 db at 1000 mhz ?? 0.65 db at 2000 mhz ?? isolation ?? 34.5 db at 1000 mhz ?? 25 db at 2000 mhz ?? typical input 1 db compression point of +32 dbm ?? package type: 6-lead sc-70 figure 2. package type 6-lead sc-70 2 f r 1 f r rfc cmos control driver esd esd esd v2 v2
product specification PE4273 page 2 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions parameter conditions typical units operation frequency 5 - 3000 mhz mhz insertion loss 1000 mhz 2000 mhz 0.50 0.65 db db isolation (rfc - rf1/rf2) 1000 mhz 2000 mhz 34.5 25 db db return loss 1000 mhz 2000 mhz 18.5 14 db db ?on? switching time 2 50% ctrl to 0.1 db of final value, 1 ghz 0.725 s ?off? switching time 2 50% ctrl to 25 db isolation, 1 ghz 0.625 s video feedthrough 1,2 < 2 mv pp input 1 db compression 2 5 mhz 1000 mhz 29 32 dbm dbm input ip3 2 5 mhz, 19 dbm input power 1000 mhz, 19 dbm input power 54 53 dbm dbm isolation (rf1 - rf2) 1000 mhz 2000 mhz 40.5 28 db db min 5 32.5 23 38.5 26 28 30 max 3000 0.60 0.75 1.5 1.3 table 1. electrical specifications @ +25c, v dd = 3v (z s = z l = 75 ? ) notes: 1. measured with a 1 ns risetime, 0/3 v pulse and 500 mhz bandwidth 2. measured in a 50 ? system
product specification PE4273 page 3 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com table 2. pin descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4 . latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 3. dc electrical specifications figure 3. pin configuration (top view) 1 2 3 4 5 6 v2 rfc v1 rf1 gnd rf2 273 pin 1 pin no. pin name description 1 rf1 rf port1 1 2 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 3 rf2 rf port2 1 4 v1 switch control input, cmos logic level. 5 rfc rf common 1 6 v2 this pin supports tw o interface options: single-pin control mode . a nominal 3-volt supply connection is required. complementary-pin control mode . a com- plementary cmos control signal to v1 is supplied to this pin. symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t op operating temperature range -40 85 c p in input power (50 ? ) 100 - 3000 mhz 5 - 100 mhz +34 +32 dbm dbm v esd esd voltage (hbm, ml_std 883 method 3015.7) 1500 v esd voltage (mm, jedec, jesd22-a114-b) 100 v parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current (v1 = 3v, v2= 3v) 8 50 a control voltage high 0.7x v dd v control voltage low 0.3x v dd v note: 1. all rf pins must be dc blocked with an external series capacitor or held at 0 vdc absolute maximum ratings are those values listed in the above table. exceeding these values may cause permanent device damage. functional operation should be restricted to the limits in the dc electrical specifications table. exposure to absolute maximum ratings for extended periods may affect device reliability.
product specification PE4273 page 4 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions control voltages signal path pin 6 (v2) = v dd pin 4 (v1) = high rfc to rf1 pin 6 (v2) = v dd pin 4 (v1) = low rfc to rf2 table 5. single-pin control logic truth table table 6. complementary-pin control logic truth table control voltages signal path pin 6 (v2) = low pin 4 (v1) = high rfc to rf1 pin 6 (v2) = high pin 4 (v1) = low rfc to rf2 control logic input the PE4273 is a versatile rf cmos switch that supports two operating control modes; single-pin control mode and complementary-pin control mode. single-pin control mode enables the switch to operate with a single control pin (pin 4) supporting a +3-volt cmos logic input, and requires a dedicated +3-volt power supply connection (pin 6). this mode of operation reduces the number of control lines required and simplifies the switch control interface typically derived from a cmos processor i/o port . complementary-pin control mode allows the switch to operate using complementary control pins v1 and v2 (pins 4 and 6), that can be directly driven by +3-volt cmos logic or a suitable processor i/o port. this enables the PE4273 to operate in positive control voltage mode within the PE4273 operating limits. figure 4. maximum operating input power 1 note: 1. operating within dc limits ( table 3 )
product specification PE4273 page 5 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com evaluation kit the spdt switch evaluation kit board was designed to ease customer evaluation of the PE4273 spdt switch. the rf common port is connected through a 75 ? transmission line to the bottom f connector, j2. port 1 and port 2 are connected through 75 ? transmission lines to two f connectors on either side of the board, j3 and j1. a through transmission line connects f connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide with gr ound plane model using a trace width of 0.021? , trace gaps of 0.030?, dielectric thickness of 0.028?, copper thickness of 0.0021? and r of 4.3. j6 and j7 provide a means for controlling the dc inputs to the device. t he lower left header (j6) is connected to the device v1 input. the lower right header (j7) is connect ed to the device v2 input. series resistors (r1 and r2) are provided to reduce the package resonance between rf and dc lines. footprints for decoupling capacitors (100 pf) are provided on both v1 and v2 traces. it is the responsibility of the cust omer to determine proper supply decoupling for thei r design application. removing these components from the evaluation board has not been shown to degrade rf performance. figure 5. evaluation board layouts peregrine specification 101/0245
product specification PE4273 page 6 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions figure 6. evaluation board schematic peregrine specification 102/0311
product specification PE4273 page 7 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com typical performance data figure 8. isolation: rf1 - rf2 @ 3.0v figure 10. isolation: rfc - rf1/rf2 @ 3.0v figure 7. isolation: rf1 - rf2 @ 25c figure 9. isolation: rfc - rf1/rf2 @ 25c
product specification PE4273 page 8 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions typical performance data figure 11. insertion loss @ 25c figure 12. insertion loss @ 3.0v figure 13. return loss: rf1/rf2 @ 25c figure 14. return loss: rf1/rf2 @ 3.0v
product specification PE4273 page 9 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com figure 16. return loss: rfc/rf1 @ 3.0v typical performance data figure 18. return loss: rfc/rf2 @ 3.0v figure 15. return loss: rfc/rf1 @ 25c figure 17. return loss: rfc/rf2 @ 25c
product specification PE4273 page 10 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions figure 19. input 1 db compression and iip3 typical performance data
product specification PE4273 page 11 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 www.psemi.com figure 20. package drawing ? 6-lead sc-70 1.80 2.20 0.65 bsc 1.80 2.40 1.15 1.35 0.15 0.30 0.80 1.10 0.80 1.00 0.10 0.30 0.10 0.40 0.10 0.18 0.00 0.10
product specification PE4273 page 12 of 12 ?2005-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0174-05 ultracmos ? rfic solutions table 7. ordering information order code part marking description package shipping method 4273-00 PE4273-ek PE4273-06sc70-ek evaluation kit 1 / box 4273-51 273 PE4273g-06sc70-7680a green 6-lead sc-70 7680 units / canister 4273-52 273 PE4273g-06sc70-3000c green 6-lead sc-70 3000 units / t&r figure 21. tape and reel specifications pin 1 tape feed direction advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com .

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